It must be stable before deasserting PERST# (pin_perst).
For CvP, the IO image is programmed first, then the Linkup sequence is performed after PERST# is released.
Refclk to the device must be stable before this PERST# is released.
Please also refer to the following Knowledge Base articles
When using the Arria® 10 PCIe* Hard IP in CvP or Autonomous mode, can the PLLs or transceivers be recalibrated in user mode if the reference clock is not stable during power up.
https://community.altera.com/kb/knowledge-base/when-using-the-intel%c2%ae-arria%c2%ae-10-pcie-hard-ip-in-cvp-or-autonomous-mode-can-the-p/346366
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Category: PCI-Express
Tools:-
Device: Arria® 10