The input clocks (rx_inclock/tx_inclock) for ALTLVDS_RX and ALTLVDS_TX must be the same clock source.
Even if the internal counter parameters of each PLL are the same, they will not be shared if the input clocks are driven by different sources.
This is also described in the user manual.
For PLL merging to happen, the input clocks and the settings on the outputs must be identical.
LVDS SERDES Transmitter / Receiver IP Cores User Guide
1.1.1. Resource Utilization and Performance
(under Resource Utilization and Performance)
If the LVDS PLL sharing is successful, the following message will appear in the compilation report.
ID:176132 Successfully merged PLL <name> and PLL <name>
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Category: IP (Other)
Tools: Quartus® Prime
Device: -