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In a design using the MAX® 10 PLL, a non-clock signal pll_lock_sync was reported in the Unconstrained Paths => Clock Status Summary of the timing analysis. Why was this signal recognized as a clock when it is a Locked signal of the PLL?

In a design using the MAX® 10 PLL, a non-clock signal pll_lock_sync was reported in the Unconstrained Paths => Clock Status Summary of the timing analysis. Why was this signal recognized as a clock when it is a Locked signal of the PLL?

  • Updated

The Locked signal of the PLL is connected to the clock pin of the FF, which the Timing Analyzer recognizes as a clock.
In this case, constraints that do not allow analysis, such as set_false_path, are invalid, so the design must be changed to a configuration that does not connect to the FF clock.

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Category: Timing Constraints/Analysis
Tool: Quartus® Prime
Device: MAX® 10

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