The maximum burst length that can be set is 256.
The ID bit width is [9 bits - ceil(log2(maximum burst length))]. For example, if 128 bursts are set, the ID bit width of AXI4 that can be connected is 2 bits.
(Also, please make sure that the ID bit width does not exceed 4KB as specified in the AXI4 specification.
For details, please refer to the following documents:
High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20031.pdf
(page 49, AXI Burst Transactions section)
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Category: External Memory Interface
Tools: -
Device: Stratix® 10