Example Designs can only be generated with the "Both Base and PHY" setting.
" PHY Only" is not supported.
(Reference) JESD204B Stratix 10 FPGA IP Design Example User Guide
https://docs.altera.com/r/docs/683758/21.3/jesd204b-stratix-10-fpga-ip-design-example-user-guide/jesd204b-intel-stratix-10-fpga-ip-design-example-user-guide
(1.2.3. Supported Configurations Reference)
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Category: Transceivers
Tools: Quartus® Prime
Devices: Stratix® 10