Example Designs can only be generated with the "Both Base and PHY" setting.
" PHY Only" is not supported.
(Reference) JESD204B Intel Stratix 10 FPGA IP Design Example User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-jesd204b.pdf
(1.2.3. Supported Configurations Reference)
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Category: Transceivers
Tools: Quartus® Prime
Devices: Stratix® 10