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Is it possible to process FPGA internal pull-ups on the LVDS pins of the Cyclone® V?

Is it possible to process FPGA internal pull-ups on the LVDS pins of the Cyclone® V?

  • Updated

Although it is possible to set the weak pull-up resistor in the Quartus® Prime settings, it cannot be used when the IO Standard for the pin in question is LVDS.

Please refer to the following documents for the setting method:
https://www.macnica.co.jp/business/semiconductor/articles/ELS1413_Q1510_21__1.pdf
(3. Internal pull-up setting <Weak Pull- Up Resistor> item)

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Category: Specifications
Tool: Quartus® Prime
Device: Cyclone® V

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