How do I access the Slave inside Platform Designer from an external CPU using the SPI Slave to Avalon Master Bridge Core?

Please refer to the following sample for implementation.

SPI Slave to Avalon Master Bridge Design Example 
 

Please refer to the following document for protocol details. 
(Reference) Embedded Peripherals IP User Guide 

4. SPI Agent/JTAG to Avalon Host Bridge Cores
 

-------------------- 
Category: Quartus® Prime (Platform Designer) 
Tools: Quartus® Prime 
Devices: -