When simulating ALTLVDS_RX IP at the RTL level, an error occurs in the "lvds_rx_reg_setting" parameter. (Both VHDL/Verilog).

If the simulator is ModelSim®, the following error occurs
<Verilog HDL>
Error (suppressible): (vsim-10000) Unresolved defparam reference to 'lvds_rx_reg_setting' in ALTLVDS_RX_component.lvds_rx _reg_setting.

<VHDL>

• Error: (vsim-3733) No default binding for component instance 'ALTLVDS_RX_component'.
  The following component generic is not on the entity:
  lvds_rx_ reg_setting

This error occurs on ALTLVDS_RX IPs created with Quartus® Prime 19.1 or later.
Workarounds include the following

<Verilog HDL>
・ Add the supress option when executing vsim. (* ModelSim limited workaround)
e.g.)
vsim -suppress 10000

　or

　In the .v generated by ALTLVDS_RX IP, remove (or comment out) the "lvds_rx_reg_setting" parameter and use it.
　　Example)
// ALTLVDS_RX_component.lvds_rx_reg_setting = "ON",.

<In case of VHDL>
- In the .vhd generated by ALTLVDS_RX IP, delete (or comment out) the following two parameters "lvds_rx_reg_setting" and use them.
　　e.g.)
--lvds_rx_reg_setting : STRING;
and
--lvds_rx_reg_setting => "ON",.

Please note that no long-term corrective action for this problem has yet been obtained.
Until then, please use one of the above methods to work around this issue.

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Category: IP (Other) / Simulation
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