FAQ

• If I want to output multiple clocks from the PLL used in LVDS, can I configure it only in External PLL Mode?
• I am using Cyclone® V SoC. I input the following command in UBOOT, but the MDIO signal of EMAC0 is not output.
• When creating a POF file from an SOF file using the Convert Programming File function, I enabled the "Create config data RPD" checkbox to create an RPD file. Is the checksum information shown in the .map file for the RPD file?
• I have generated a single-port RAM and am running an RTL simulation, but "altera_syncram" is not found in the "altera_mf.v" module, resulting in a simulation error. Please tell me where to find the library file where "altera_syncram" is defined.
• When running a design that uses PCIe (PCI-Express) IP (IP_Compiler for PCI Express) targeting Cyclone® IV through Platform Designer in Quartus® Prime Standard Edtion ver19.1 Generate HDL in Platform Designer in Quartus® Prime Standard Edition ver 19.1.
• Error when generating an Example Design for HDMI Intel FPGA IP in Quartus® Prime Pro Edition v20.2.
• An error occurs when creating and compiling a CvP (Configuration via Protocol) update revision.
• On FPGAs below 20nm process, even if I generate a simulation model for ALTERA_FP_FUNCTIONS in Verilog, the lower modules are generated as VHDL files.
• When ALTMULT_ACCUM is used to calculate ∑ (sum of sums of products and sums of squares) 1000 by 1000, please tell me how to control the start and end of the calculation for ∑.
• The "Simulate loss" setting is missing from the DDRx Batch Wizard in HyperLynx VX2.5 and later.
• In the Cyclone® V Device Datasheet, the QSPI controller timings say "Tqspi_clk", which clock is this referring to?
• There is a tCS min (CS# High Time (Read Instructions), CS# High Time (Program/Erase)) timing specification on the QSPI Flash side, but there is no such timing specification on the Cyclone® V SoC side. How can I fulfill this requirement?
• When I run RTL simulation with Nativelink on a design using DDR3 SDRAM Controller MegaCore supporting UniPHY, I get an error.
• I am using PIO Core to interrupt a Nios® II CPU, is there a register that I can check to see if an interrupt is occurring?
• On a Cyclone® V SoC, I am trying to route an HPS SPI master device to an FPGA, but there is no sclk.
• What is the use of the a10_reconfig_arbiter module in the Example Design generated by SDI IP? Is this module required?
• Generating FP_FUNCTIONS Intel FPGA IP on Quartus® Prime Standard Edition 20.1 causes an error.
• On a Cyclone® V SoC, how do I connect each port when routing a Hard Processor System (HPS) SPI master to an FPGA?
• In the "SDRAM Controller Core" section of the Embedded Peripherals IP User Guide, "FPGA I/O Timing Parameters" is shown. What are the other timing parameters for different tCLK values?
• I am trying to route an HPS SPI master to an FPGA on an Arria® V SoC, but I don't know how to connect each port.
• On an Arria® V SoC, I am trying to route an HPS SPI master device to an FPGA, but there is no sclk.
• Altera® HLS compiler installer is missing from Quartus® Prime Standard Edition v20.1.
• Do you have any reference materials on software development for Nios® II?
• When using EMIF (External Memory Interface) IP on Arria® 10, is it necessary to set the I/O Standard in the Assignment Editor for the external pins for EMIF (DQ, DQS, Add/Cmd, etc.)?
• We are working on capacitor selection with the PDN Tool, how do we register the values calculated from the EPE (Early Power Estimator) into the PDN Tool?
• When I run Run As in Nios® II SBT (SOftware Build Tools for Eclipse), the software runs but the printf statement does not appear on the Nios II Command Shell.
• How do I write JIC (JTAG Indirect Configuration) with the Nios® II Command shell?
• What is the difference between the two types of Nios® II processors, Fast and Economy?
• How do I exclude a node in the Signal Tap from the analysis by setting it in the timing constraints file (sdc)?
• There is no "Generate Value Change Dump file script" option in the Pro Edition that allows Quartus® Prime to generate a script to generate a VCD for an EDA simulator such as ModelSim®. How can I set this up?