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On FPGAs below 20nm process, even if I generate a simulation model for ALTERA_FP_FUNCTIONS in Verilog, the lower modules are generated as VHDL files.

On FPGAs below 20nm process, even if I generate a simulation model for ALTERA_FP_FUNCTIONS in Verilog, the lower modules are generated as VHDL files.

  • Updated

RTL level simulation of ALTERA_FP_FUNCTIONS IP (FP_FUNCTIONS Intel FPGA IP) requires a simulator that supports both languages. 
Therefore, it is not available in VCS. Please consider using a Language Mixed simulator such as 
VCS MX. 
Alternatively, you can use ModelSim-Intel FPGA Starter Edition, which is provided free of charge by Intel PSG, as it is a dual-language simulator.

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Category: Simulation 
Tools: Quartus® Prime 
Devices: Arria® 10 FPGA

 

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