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In the "SDRAM Controller Core" section of the Embedded Peripherals IP User Guide, "FPGA I/O Timing Parameters" is shown. What are the other timing parameters for different tCLK values?

In the "SDRAM Controller Core" section of the Embedded Peripherals IP User Guide, "FPGA I/O Timing Parameters" is shown. What are the other timing parameters for different tCLK values?

  • Updated

Embedded Peripherals IP User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf

In addition to tCLK, the following four timing parameters are required in "FPGA I/O Timing Parameters":
1. tCO_MIN
2. tCO_MAX
3. tH_MAX
4. tSH_MAX

These values should be referred to and set in the following sections of TimeQuest.
　tSU/tH/tCO : Refer to Report Datasheet of TimeQuest
MAX : Set Operating Condition to 6_slow_1100mv_85c
MIN : Set Operating Condition to MIN_fast_1100mv_0c

The specifics are as follows:
1. tCO_MIN
Set the Operating Condition to MIN_fast_1100mv_0c
=> Set the Operating Condition to the lowest value of SDRAM signal in "Minimum Clock to Output Times" from TimeQuest's Report Datasheet. 2. tCO_MAX => Set MIN_fast_1100mv_0c.

2. tCO_MAX
Set Operating Condition to 6_slow_1100mv_85c
=> Use the highest value of SDRAM signal in "Clock to Output Times" from TimeQuest's Report Datasheet.

3. tH_MAX
Set Operating Condition to 6_slow_1100mv_85c
=> Adopt the highest value of SDRAM signal in "Hold Times" from TimeQuest's Report Datasheet.

4. tSH_MAX
Set Operating Condition to 6_slow_1100mv_85c
=> Use the highest value of SDRAM signal in "Setup Times" from TimeQuest's Report Datasheet

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Category: External Memory Interface
Tools: Quartus® Prime
Devices: -