FAQ

• How can I set a constraint in Quartus® Prime Pro Edition to generate .rbf at compile time (Assembler time) that I can specify in Quartus® Prime Standard?
• I performed IO PLL reconfiguration on Arria® 10, but the phase may be out of phase. Please let me know how to solve this problem.
• What happens when writing to the same address from both Port A and Port B of True Dual Port RAM with Cyclone® V?
• I installed the WSL environment for Quartus® Prime Pro Edition v20.1, but when I run nios2-terminal in the Nios® II Command Shell, I get an error.
• What is the power-up time requirement when using Active Serial Fast Mode with Stratix® 10?
• After writing a non-volatile AES key to an Arria® 10 SoC device, I programmed it into the configuration ROM using a jic file, but the configuration fails. What could be the cause?
• Are there any PCB design rules for Pad on Via in Altera FPGAs?
• The following Warning occurs in the Quartus® Prime Fitter regarding PLL. Please let me know the countermeasure.
• I use SDI II IP with Arria® 10, does it also support SD-SDI?
• Do I need a Nios® II license to Build or Debug with the Nios® II Software Build Tools (SBT)?
• I have enabled Prarallel comiplation in Quartus® Prime, but Analysis & synthesis reports that it is not working with multicore. Under what conditions does multicore work?
• Compiling qts_pam4_com from the Example Design included in the installer for the Stratix® 10 TX FPGA Signal Integrity Development Kit causes errors in logic synthesis.
• In Cyclone® V, if only one lane is physically connected in the configuration of Board A: TX x 2 Lanes => Board B: RX x 1 Lane x 2 pieces using Custom PHY, the device will not operate properly.
• I have set MAX_FANOUT for a clear signal in Quartus® Prime, but it is ignored.
• How do I run a PCI-Express (PCIe) Gen3 Root Port simulation on an Arria® 10 device?
• Eclipse can be started successfully from the SoC EDS Command Shell in Quartus® Prime Pro Edition ver. 19.3, but bsp-editor cannot be started.
• For the Arria® 10 SDI II IP, are there any status signals other than rx_is_lockedtodata that can be used to determine if the SDI signal is disconnected?
• I would like to access the Cyclone® V SoC with spim0 of the SPI Master Module.
• I am configuring a QDR II SRAM in an Arria® 10. Can the Address/Command pins be placed freely at this time?
• Can I use Triple Rate (up to 3G-SDI) and change the format received for each transceiver channel?
• Regarding the Cyclone® V SoC Address Map, 0x0000_0000 to 0x1000_0000 is BOOT ROM+ON CHIP RAM at startup, and after PREBOOT, when UBOOT starts, is it REMAP'd and changed to SDRAM space from 0x0000_00000? Is it?
• When using Cyclone® V DDR3 EMIF (External Memory Interface) IP, how can I check the value set in the mode register (MR0-3) at the start of user mode?
• When using Cyclone® V DDR3 EMIF (External Memory Interface) IP, is it possible to check the value set in the mode register (MR0-3) at the start of user mode in simulation or on the actual device?
• The Stratix® 10 Development Kit comes with three types of memory: DDR4/DDR3/RLDRAM.
• I am using a Hard Processor System (HPS) DDR memory controller; what setting is reflected in the mode register of the DDR memory?
• What image formats are used for inference in the OpenVINO™ toolkit?
• I am evaluating OpenCL™ on an Intel® Stratix® 10 evaluation kit. When I set it to PCI-Express 16 lanes and check with "aocl diagnose", I get the message "PCIe dev_id = 5170, bus:slot.func = 01:00.00, Gen3 x8" which is 8 lanes.
• On a system running Linux, can I use the ALT_WRITE_WORD / ALT_READ_WORD API functions described in socal.h of SoC EDS to read/write registers implemented in the FPGA part?
• Is it possible to use the IP provided by Quartus® Prime for OpenCL™ kernel creation?
• What is the difference between development using the Intel® HLS compiler and development using the Intel® FPGA SDK for OpenCL™?