FAQ

• Can I use the OpenVINO™ toolkit to run the OpenCV library on FPGA circuitry?
• How do I change the baud rate setting for the UART in the Hard Processor System (HPS) of the Cyclone® V SoC while the Preloader is running?
• Does the simulation script generated by Tools menu > Generate Simulator Setup Script for IP in Quartus® Prime Pro Edition include the user design files in the project?
• I would like to know the Latency of the Transceiver Block of an Arria® 10 device.
• What version of Microsoft Visual Studio is required for the Intel® HLS compiler?
• What version of C++ compiler is required for the Intel® HLS compiler?
• I am using Transceiver PHY IP with Stratix® 10, but when I configure VOD in QSF, an error occurs in Fitter.
• When I create a new ALTFP_DIV IP in Quartus® Prime Standard 19.1 and compile it, I get the following error
• I am using a PCI-Express (PCIe) IP (Avalon®-MM configuration) with a Cyclone® V device. When is the Avalon-MM Wait signal negated when a Memory Write request is performed? Does this include ACK or other responses from the peer device?
• What is the UMask (acceptance mask) feature of the CAN controller with integrated Cyclone® V SoC?
• I am verifying Triple-Speed Ethernet (TSE) IP with the Arria® V GX Starter Development Kit, but outgoing packets are not being output from the MAC to the PHY.
• I am using a Cyclone® V SoC with Linux in a QSPI boot configuration. After changing the Kernel version to a recent version (4.14.73-ltsi), Read access to the QSPI Flash from Linux no longer works as expected.
• If I enable the filtering function of the CAN controller built into the Cyclone® V SoC, how many filtering IDs can I set?
• In Nios® II Software Build Tools (SBT) for Eclipse, after Build, the Problems window shows an error, but the console window shows a message that the compilation finished successfully. Which is correct?
• How should I use the DisplayPort IP non-GPU mode and GPU mode settings?
• I am using PCI-Express (PCIe) with DMA IP on Arria® 10, but I get errors in compilation. What is the workaround?
• We are designing a PCI-Express (PCIe) Root Port - Endpoint (using Avalon-ST interface) with two Arria® 10 devices facing each other. Is it possible for the Endpoint to get information about the Configuration space set for itself?
• I am using Linux on a Cyclone® V SoC with a QSPI boot configuration, and the following log is displayed when restarting after a Watchdog Timer Timeout has occurred. Please let me know the cause.
• Regarding the MMU settings for the Cyclone® V SoC (Cortex-A9), what does Inner / Outer mean, which can be selected as the Cache attribute setting?
• I am using Native PHY with Arria® 10. I would like to change the Analog Parameter, can I do this on the IP generation screen?
• If the MAX® 10's JTAGEN pin is enabled and switched High / Low in user mode, can it be switched to User I/O or JTAG pins?
• Can I use the DEV_CLRn pin to reset the PLL or hard IP?
• What is the value of "Output Slack" in Synchronizer Chain #"Number" displayed when generating a Metastability report in Quartus® Prime's Timing Analyzer?
• I am using a Mentor Graphics simulator. Which version should I use to simulate an Intel® FPGA design?
• Using the sqrt_fixed function provided for the ac_fixed data type in the Intel HLS compiler will result in an error when the HLS compiler is run if the input exceeds 32 bits.
• The quartus_cpf command (Convert Programming File) has clock_divisor and clock_frequency as option file settings (-o). Can I use these options to change the frequency of the configuration clock without recompiling?
• Regarding DisplayPort IP error for Secondary Stream, if IP detects an error, can it be confirmed by some signal? Is there an error correction function?
• If [Current Strength] is set to "Default" in a Quartus® Prime synthesis report, for example, what exactly is the mA set to? For example, the DQ/DQS signal on the External Memory Interface (EMIF) looks like this.
• I am considering Configuration via Protocol (CvP) for Stratix® 10 devices. Can it support Autonomous mode, etc.?
• The Quartus® Prime report for the Tx Current strength value for High Speed Differential I/O in Arria® 10 shows the [Current Strength] of the pin as "Default", but what is the mA value? What is the value?