When implementing CvP, the Periphery image is written first using .periph.jic, which contains all the PCI-Express Hard IP (PCIe HIP) information for the device.
Note that the only PCIe HIP block that is supported by CvP is the bottom left corner of the device.
(Reference) Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-s10-cvp.pdf
(CvP System section)
Note that the Stratix® 10 device does not have a configuration item for Autonomous mode, but it is enabled by default for all PCIe HIPs.
However, only the bottom left HIP Block, which also supports CvP, can meet the 100ms PCIe specification.
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Category: PCI-Express
Tool: Quartus® Prime
Device: Stratix® 10