Skip to main content

We are designing a PCI-Express (PCIe) Root Port - Endpoint (using Avalon-ST interface) with two Arria® 10 devices facing each other. Is it possible for the Endpoint to get information about the Configuration space set for itself?

We are designing a PCI-Express (PCIe) Root Port - Endpoint (using Avalon-ST interface) with two Arria® 10 devices facing each other. Is it possible for the Endpoint to get information about the Configuration space set for itself?

  • Updated

In a PCIe system, a Configuration Transaction is basically issued from the Root Port side and a Configuration Read/Write is performed on the
Endpoint side, but an interface called LMI is available for debugging purposes.

（For reference: Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-ST Interface for PCI Express* User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf
(5.11. LMI Signals rope)

This signal can be used to access the Configuration space.
This signal should be used in Read Only mode.

--------------------
Category: PCI-Express
Tools: -
Device: Arria® 10

Related articles