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I am using a PCI-Express (PCIe) IP (Avalon®-MM configuration) with a Cyclone® V device. When is the Avalon-MM Wait signal negated when a Memory Write request is performed? Does this include ACK or other responses from the peer device?

I am using a PCI-Express (PCIe) IP (Avalon®-MM configuration) with a Cyclone® V device. When is the Avalon-MM Wait signal negated when a Memory Write request is performed? Does this include ACK or other responses from the peer device?

  • Updated

Negated when the Avalon-MM port of the PCIe IP receives a Write request from the Master side.
Does not include the time about the ACK of the peer device.

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Category: PCI-Express
Tools:-
Device: Cyclone® V

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