FAQ

• Assuming that ref_clk is in normal as the cause of the internal PLL not locking, is there anything other than the power supply that could be causing this?
• In Quartus® Prime Pro Edition ver. 18.1.0, there is an error generating a PCI-Express Hard IP Example Design for Stratix® 10.
• I am implementing PCI-Express Avalon-ST IP on an Arria® 10 GX and I cannot find the Byte Enable signal that was available on the previous device.
• Does the Arria® V GX support PCI-Express Lane Reversal functionality? And does it support Gen2 x2 configuration?
• The initialization time (from CONF_DONE high to INIT_DONE high) takes more than several tens of ms depending on the ambient temperature. Is it possible for the temperature to cause such a long delay?
• Is there anything I should pay attention to when deciding the placement of the Transceiver's Refclk in the Stratix® 10 FPGA?
• When using PCI-Express with Stratix® 10, do I use fPLL or ATX PLL?
• What does the Number of Command Port on the HMC (Hard Memory Controller) sheet on the Early Power Estimate (EPE) sheet for Cyclone® V mean?
• What flash devices can be used as configuration ROM for Intel® FPGAs?
• Where can I find the release notes for Quartus® Prime Pro Edition v19.1?
• The Parallel Flash Loader (PFL) user guide states that MT25Q is supported. Can I use MT25Q-L?
• The Knowledge Database (KDB) states that pgm_allow_mt25q=on must be added to the ini file to use the MT25Q flash device as configuration ROM, but is this ini file required for any version?
• Arria® 10 device failed to configure in AS mode and JTAG access was lost.
• Is it possible to calculate the temperature of a substrate using the CTM model for CFD analysis provided in Straitx® 10?
• Generating a simulation model of ALTCLKCTRL IP in VHDL and compiling it in ModelSim results in an error.
• Using a Transceiver Block with Cyclone® V. Which has better performance, the case where Refclk is input by using an external PLL to generate the desired frequency or the case where Refclk is input directly from the pins at the desired frequency?
• What is the default Preset value for PCI-Express (PCIe) Hard IP on Stratix® V? Can the Preset value be changed?
• When I use a symbol in the Quartus® Prime schematic editor, the pin name display in the symbol is cut off. What is the workaround?
• Why is there a difference between at Pin and at Die observation points in board simulation using IBIS?
• In board simulation using IBIS, there are "at Pin" and "at Die" observation points, which waveform should be observed?
• How can I access the AS configuration ROM connected to the Cyclone® V device from an external processor?
• What is the PIPE interface version of the PCI-Express (PCIe) IP on the Stratix® 10?
• Is it possible to use Dual-Port (2-Port) RAM with Error Correction Code (ECC) capability using an "On-Chip Memory (RAM or ROM)" core in a MAX® 10 FPGA?
• After replacing the Arria® 10 configuration ROM from EPCQL256 to MX25U256, configuration is no longer possible.
• Is it possible to enable/disable Quartus® Prime floating licenses on a per-user basis?
• When changing the TCK clock frequency with the jtagconfig command, the message "No parameter named JtagClock" appears and the frequency cannot be changed.
• RAM is assigned to logic in Stratix® 10.
• I have added the IP generated by the Altera® HLS compiler to the Platform Designer system and generated a simulation model (VHDL). When I simulate in ModelSim, the IP outputs indeterminate values.
• Does Stratix® 10 support Bus LVDS?
• Is there a way to trigger the Signal Tap at the same time as a break on the Nios® II SBT for Eclipse?