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Is there anything I should pay attention to when deciding the placement of the Transceiver's Refclk in the Stratix® 10 FPGA?

Is there anything I should pay attention to when deciding the placement of the Transceiver's Refclk in the Stratix® 10 FPGA?

  • Updated

For the Reference Clock, check the following section of the User Guide.

(Reference) Intel® Stratix® 10 L- and H-Tile Transceiver PHY User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf
- 1.3.5.2. Input Reference Clock Sources
- 3.2.

Also, please actually create a sample with Quartus® Prime, place the terminals and check if it is possible to place them.

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Category: PCI-Express
Tools: Quartus® Prime
Devices: -

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