Is there anything I should pay attention to when deciding the placement of the Transceiver's Refclk in the Stratix® 10 FPGA?

For the Reference Clock, check the following section of the User Guide.

(Reference)  L- and H-Tile Transceiver PHY User Guide
　- 1.3.5.2. Input Reference Clock Sources
　- 3.2. Input Reference Clock Sources

Also, please actually create a sample with Quartus® Prime, place the terminals and check if it is possible to place them.

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Category: PCI-Express 
Tools: Quartus® Prime 
Devices: -