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Is it possible to use Dual-Port (2-Port) RAM with Error Correction Code (ECC) capability using an "On-Chip Memory (RAM or ROM)" core in a MAX® 10 FPGA?

Is it possible to use Dual-Port (2-Port) RAM with Error Correction Code (ECC) capability using an "On-Chip Memory (RAM or ROM)" core in a MAX® 10 FPGA?

  • Updated

RAM: The M144K and M20K can be optionally equipped with ECC functionality for 2-Port, so the following devices can be supported. 
Arria II GZ 
- Stratix IV (M144K) 
- Cyclone 10 GX 
- Arria 10 
- Stratix V (M20K)

(Reference) 
Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide 
https://docs.altera.com/r/docs/683240/17.0/embedded-memory-ram-1-port-ram-2-port-rom-1-port-and-rom-2-port-user-guide/about-embedded-memory-ip-cores

In MAX® 10, the option of ECC can be selected in Platform Designer, but in practice it is necessary to implement and use "ALTECC" encoders and decoders externally.

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Category: Specification 
Tool: Quartus® Prime 
Device: MAX® 10

 

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