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Is it possible to use Dual-Port (2-Port) RAM with Error Correction Code (ECC) capability using an "On-Chip Memory (RAM or ROM)" core in a MAX® 10 FPGA?

Is it possible to use Dual-Port (2-Port) RAM with Error Correction Code (ECC) capability using an "On-Chip Memory (RAM or ROM)" core in a MAX® 10 FPGA?