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When using PCI-Express with Stratix® 10, do I use fPLL or ATX PLL?

When using PCI-Express with Stratix® 10, do I use fPLL or ATX PLL?

  • Updated

Depending on the rate of the PCIe IP, for example, Gen3 uses both fPLL (Gen1/Gen2) and ATX PLL (Gen3). 
These are automatically configured when the IP is implemented and the placement can be viewed in the Fitter Report and Pin Planner. 
There is no need for the user to place them in the design as with the Native PHY.

(Document) L- and H-Tile Avalon Streaming and Single Root I/O Virtualization (SR-IOV) IP for PCI Express User Guide 
⇒ 5.6. Channel Layout and PLL Usage

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Category: PCI-Express 
Tools: Quartus® Prime 
Device: Stratix® 10

 

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