Depending on the rate of the PCIe IP, for example, Gen3 uses both fPLL (Gen1/Gen2) and ATX PLL (Gen3).
These are automatically configured when the IP is implemented and the placement can be viewed in the Fitter Report and Pin Planner.
There is no need for the user to place them in the design as with the Native PHY.
（Intel® Stratix® 10 Avalon®-ST and Single Root I/O Virtualization (SR-IOV) Interface for PCI Express* Solutions User Guide
⇒ https://www.intel. com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avst.pdf#page=54
(Channel Layout and PLL Usage section)
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Category: PCI-Express
Tools: Quartus® Prime
Device: Stratix® 10