Arria® V devices are supported for Lane Reversal.
(Reference) Arria V Avalon-MM Interface for PCIe Solutions User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a5_pcie_avmm.pdf
(see Physical Layer and Lane Initialization and Reversal sections)
Gen2 x2 is supported by Avalon-ST, but not by Avalon-MM.
（Intel® FPGA IP for PCI Express*
https://www.intel.com/content/www/us/en/programmable/products/intellectual-property/ip/interface-protocols/m-pci-express-protocol.html#device-support
(see Device Support tab)
It is possible to generate IP in a x4 configuration and use it as x2 in the downlink.
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Category: PCI-Express
Tools: Quartus® Prime
Device: Arria® V