<error message>
Error: //<altclkctrl_ip_name>/simulation/submodules/<altclkctrl_ip_name>_altclkctrl_0.vhd(148): near "BEGIN": ( vcom-1576) expecting END.
Due to a defect in the VHDL simulation model of the ALTCLKCTRL IP, compiling it with a simulator such as ModelSim will result in an error.
If you encounter errors similar to the above, please follow the workaround below.
Target device: ALL FPGA
Target tool: Pro 19.1 / Standard 18.1 / Lite 18.1
Failure Cause]
[Pro Edition]
//<altclkctrl_ip_name>/altclkctrl_*/sim/<altclkctrl_ip_name>_altclkctrl_*_*.vhd
There is no END COMPONENT declaration for <altclkctrl_ip_name>_altclkctrl_**_*_sub, which is declared COMPONENT in the above model.
[Standard/Lite Edition]
//<altclkctrl_ip_name>/simulation/submodules/<altclkctrl_ip_name>_altclkctrl_0.vhd
There is no END COMPONENT declaration for <altclkctrl_ip_name>_altclkctrl_0_sub, which is declared COMPONENT in the above model.
Workaround]
Please add the following at appropriate places.
END COMPONENT;.
After that, please compile with the simulator.
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Category: Simulation
Tools: ModelSim® / Quartus® Prime
Device: -