It is set to Preset 7 or 8.
For example, the Gen3 x8 Avalon-ST design looks like this
top > synthesis > submodules
filename : altpcie_sv_hip_ast_hwtcl.v
line 1376 Please check the following.
↓
localparam [17:0]gen3_coeff_1 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_1_hwtcl [17:0]: 18'h7;
. .
localparam [17:0]gen3_coeff_2 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_2_hwtcl [17:0]: 18'h8;
... .
localparam [17:0]gen3_coeff_3 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_3_hwtcl [17:0]: 18'h7;
... .
localparam [17:0]gen3_coeff_4 = ( hwtcl_override_g3rxcoef==1 )?gen3_coeff_4_hwtcl [17:0]: 18'h8;
Note that the Preset value can be changed, but the best value depends on the channel characteristics.
Please refer to the following Knowledge Database for reference.
（How to set up the Stratix V PCIe HIP to request preset 9 to improve its Gen 3 receive eye margin?
https://community.altera.com/kb/knowledge-base/how-to-set-up-the-stratix-v-pcie-hip-to-request-preset-9-to-improve-its-gen-3-re/347160
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Category: PCI-Express
Tools:-
Device: Stratix® V