FAQ

• Does Arria® 10 support ECO?
• What are the Run Length specifications and the Refclk frequencies that can be set for the Arria® 10 Transceiver CDR?
• If data is lost due to a reset of the device on the other side during data communication, is it necessary to do something about it, such as putting in rx_analogreset, performing recalibration, resetting the entire Transceiver, etc.?
• Is there a way to run a simulation in Modelsim® and later display signals that were not displayed?
• I am estimating power consumption using the Early Power Estimator (EPE) sheet in Cyclone® V, but the estimated result for the IO portion of the Hard Memory Controller (HMC) is zero. Am I missing a setting?
• It seems that DCLK continues to be output even after AS configuration is completed. When accessing the configuration ROM using ASMI IP in user mode, which is used, clkin or DCLK input to IP?
• How can I use my own stimulus input file in a MAX® 10 ADC simulation?
• If the speed grade of the memory model number is different from the actual SDRAM operating frequency, what settings should be put in "Memory Parameter" and "Memory Timing" in the SDRAM Controller IP settings?
• How do I configure an FPGA from a TI DSP using a parallel bus for general purpose flash?
• I am trying to verify 100G Ether on a Stratix® 10 SoC (H-Tile), is the QSFP28 connector connected to the Ethernet Hard IP?
• When selecting a pof/jic file for MT25Q flash devices in the Programmer, I get the error "File <name> is corrupted".
• Regarding the method of writing eMMC for booting Cyclone® V SoC, does the HPS Flash Programmer not support eMMC? If not, what are the writing methods available?
• We are implementing multiple PCI-Express (PCIe) Hard IPs and Transceivers in an Arria® 10 device. What, if any, precautions should be taken during startup?
• Receive descriptor RDES0 Bit7: Timestamp Available, IP Checksum Error (Type1), or Giant Frame for EMAC in HPS (Hard Processor System) Do Giant Frame errors occur?
• I am considering the Advanced Encryption Standard (AES) for design security features, which download cables can be used to write AES keys?
• I want to interface from the SFPP of the Arria® 10 SoC Development Kit with an external clock supply.
• When I run the procedure "Make Targets" => "Build" => "mem_init_generate" in the Nios® II Software Build Tools (SBT), I get the error elf2flash: Error reading boot copier and Hex Hex is not generated.
• The following error may occur when running simulation scripts (e.g. msim_setup.tcl) generated by Quartus® Prime, Platform Designer, etc. using Questa® Sim version 2019.1 or later
• How do I build the Nios® II Software Build Tools (SBT) for Eclipse (Nios® II EDS) environment in Quartus® Prime ver 19.1 or later?
• I am using PCI-Express (PCIe) IP in an Arria® 10 device under the following conditions: How do I access the DMA Descriptor Controller Register?
• In the PDN Tool, the Dynamic Current Change item is displayed as 50%, but is this based on the supply power (VRM) or the maximum current value of the user circuit?
• Can I use translator IPs for connections between Platform Desinger (formerly Qsys) and outside Platform Desinger?
• A license error occurs when accessing a machine with a node-locked license of ModelSim®-Altera® Edition via Windows remote desktop to run a simulation.
• Are there any single or double precision benchmark results on the hard processor system (HPS) side for the Cyclone® V SoC?
• In Cyclone® V SoC / Arria® V SoC, when the FPGA design is changed, a handoff file is generated.
• Is it possible to rewrite the EPCQ-A without having the configuration run at power-on?
• What Ethernet MAC interfaces can I use through the FPGA on an Arria® 10 SoC?
• Is it ok if reconfig_clk (mgmt_clk) is stopped at device startup on Stratix® 10?
• I have a PCI-Express (PCIe) implementation on an Arria® V GX. When I compile with the transceiver pins assigned, an error occurs in the Fitter.
• Is bit selection of variables possible in C++ source code for the HLS compiler?