FAQ

• Is it safe to gate pll_ref_clk at startup on Stratix® 10? Also, how do I perform a recalibration?
• I have a SODIMM connected, but the calibration fails. What could be the reason?
• I am using PCI-Express (PCIe) with Cyclone® V with the Avalon®-MM interface. The description of the RxmByteEnable signal in the user guide says "DWORD enables for write data." Is this signal not available for Read Transaction?
• For an OCT configuration such as Arria® V DDR3 controller IP (EMIF) requiring RZQ=240Ω, is there a specified accuracy for a 240Ω resistor?
• Does Cyclone® V SoC automatically generate .xml files (e.g. hps_common_board_info.xml) to be passed to DeviceTree Generator?
• How do I check the calibration report for the hard processor system (HPS) side SDRAM controller in a Cyclone® V SoC?
• I am using a PCI-Express (PCIe) Endpoint with Cyclone® V. How do I reset the IP? I would like to perform a re-link training from the endpoint side, but what kind of reset should I apply to the IP?
• When I run a co-simulation of a circuit generated by the High Level Synthesis (HLS) compiler, the generated wlf file does not reflect the clock frequency set with --clock and is set to 1 GHz.
• Can I rewrite only the CFM or UFM when programming MAX® 10?
• Are the I/O pins in the MAX® 10 configuration in the Weak-PullUp ON state? Or can the user set them as desired (Hi-Z or WeakPullUp ON) in QuartPrime settings, etc.?
• Error in loading DCFIFO during verification in Nativelink simulation environment using ModelSim®-Intel® FPGA Edition.
• Is it possible to use OpenCL™ to perform calculations with half-precision floating point numbers such as int8 and FP16 on an FPGA?
• When does the Arria® 10 temperature sensor IP (Altera Temperature Sensor) measure temperature?
• What is the Thread Capacity listed in the OpenCL™ report?
• If I change the DCLK frequency setting for configuration, do I need to recompile?
• The EN5339QI datasheet mentions MTBF, but what are the test conditions?
• When performing Remote System Upgrade on MAX® 10, is it only possible to prepare two configuration images (Factory and Application) and rewrite the Application Image? Is it possible to update with a single image?
• Are there any Tr, Tf specifications in Altera® FPGAs?
• In the RX PMA setting of the Arria® 10 GX Transceiver Block, the CTLE Mode has "Manual" and "Triggered". How should I use them?
• The following error occurs when running Design Space Explorer (DSE) II
• Is it possible to trigger reconfiguration of the Dual Configuration Altera FPGA IP Core on a MAX® 10 FPGA via the external nCONFIG pin? If so, will the config_sel setting set in the IP register be reflected?
• What precautions should I take when programming on an Arria® 10 FPGA with JAM STAPL Player?
• How do I generate a JIC file on the command line?
• I have run the i++ compilation on Ubuntu, and I get the following error: I am using Quartus® Prime Pro Edition ver. 18.1.
• Do I need a Quartus® Prime license to create a POF file containing an AES key?
• For the Custom PHY of Cyclone® V, if a unique IP is connected and used, is it necessary for the user to control and input the control codes such as COM/SKP?
• The datasheet default for RA in EP53A8LUI is 237kΩ, can I use 240kΩ?
• With Quartus® Prime ver. 17.1, an error occurs when trying to write to ROM via EP4CE75 using a JIC file.
• Should the pins marked GND in the "HMC Pin Assignment for DDR3/DDR2" section of the Pin-Outs file provided by the Hard Memory Controller (HMC) be connected to GND?
• Is an external diode required to protect EP53A8LUI against reverse voltage when power is turned off, etc.?