FAQ

• Is there a reference design for Ethernet connectivity in the Cyclone® 10 LP FPGA Evaluation Kit?
• Can I do Configuration via Protocol (CvP) with Quartus® Prime Programmer only?
• Can the DDR3 Controller core output pll_locked be used without PLL sharing? The User Guide states "This interface is enabled only when you set PLL sharing mode".
• I am performing a PCI-Express (PCIe) design using Stratix® 10 devices. We are using Quartus® Prime v18.1 Pro Edition and are experiencing a "Minimum Pulse Width" violation in our timing analysis.
• Is there any documentation on how to use Platform Designer's Address Span Extender?
• How should software handle the use of Platform Designer's Interval Timer core as a Watch Dog Timer?
• The clock frequency set by the --clock option in the High Level Synthesis (HLS) compiler is not reflected in the generated SDC file.
• Can I choose the hardware language output by the High Level Synthesis (HLS) compiler?
• Is Cyclone® 10 LP supported by the High Level Synthesis (HLS) compiler?
• How do I place an interrupt from a peripheral placed in Platform Designer and an interrupt from an HDL created outside Platform Designer on the IRQ0 port of the Hard Processor System (HPS)?
• I have a Signal Tap Logic Analyzer generated and implemented in IP Catalog, can I expand it to an STP file reflecting my settings?
• I plan to implement two External Memory Interface (EMIF) IPs. Is there anything I need to be aware of?
• What is the difference between the Abstract PHY and the regular model used to simulate the External Memory Interface (EMIF)?
• I want to measure power consumption with the Board Test System (BTS) Power Monitor using the Cyclone® V SoC Development Kit.
• Is there a way to reduce the External Memory Interface (EMIF) simulation time with Arria® 10?
• Stratix® 10 has SDM_IO[16:0] as configuration pins.
• Are there any provisions for the location of the termination resistor or the trace length to the termination resistor when connecting Cyclone® V to DDRx?
• I cannot monitor the fiftyfivenm_lcell_comb signal when simulating a .vo file of a design targeting MAX® 10 in ModelSim® - Intel FPGA Edition.
• Adding signals I want to observe to the Wave window in ModelSim® slows down the simulation speed, and removing them from the Wave window does not improve it.
• Is there any wiring guidance or provision for each trace length when Cyclone® V and DDR3 are not fly-by-connected?
• I want to specify multiple quartus.ini files. Is there a way to use both $HOME/quaruts.ini and /quartus/bin/quartus.ini?
• Where can I get an IBIS model of an Intel® FPGA?
• I have multiple versions of Quartus® Prime installed on my PC, and when I double-click on a qsf file, it launches a different version of Quartus than the version that created the corresponding qsf.
• What is the text file that is generated in the (instance name)_sim folder when the Coefficients Reload option is enabled in FIR Compiler II?
• Can I use Nios® II and Intel Serial Flash Controller II to apply Sector Protect to EPCQ128 (not A)?
• Can VCC = 0.95 V be applied to Arria® 10 -E3S devices? The datasheet reads VCC = 0.95 V can be used.
• Unable to write pof file to MAX® 10 Configuration Flash Memory (CFM).
• What is the maximum length of code words (size of one packet) that can be set in the Encoder of the Reed Solomon II IP core?
• What is the maximum operating clock for Nios® II Gen2?
• When doing a simulation involving Nios® II, is there any way to reduce the time it takes for the main() function to start?