FAQ

• I want to change the optimization level of some functions in Nios® II SBT.
• Connecting an input from the transceiver reference clock (REFCLK) pin to ALTCLKCTRL on the Cyclone® IV will result in a Fitter error.
• I am unable to download Quartus® Prime in the Download Center.
• I cannot access the License Center because I cannot sign in to My Altera.
• What is the MTBF value of EN5366QI?
• When generating in Platform Designer I get a try "Remove Dangling Connections" error.
• What sources can be used for the Reference Clock input to the TX PLL of the Cyclone® 10 GX transceiver?
• Does the switching frequency of the power supply used in MAX® 10 Single Power have to be 800kHz and 1MHz?
• If I enable the Allow Register Merging option in Settings -> Advanced Fitter Settings in Quartus® Prime, can I disable merging only certain blocks?
• When using MAX® 10, is a ferrite bead for isolate of VCCD_PLL power supply mandatory?
• I would like to verify that the Hard Processer System's SPI verification can be connected in a loopback and send/receive correctly. Can I connect the SPI interface from the Hard Processor System (HPS) and use it as a conduit in Platform Designer?
• Configuring a tri-state on a pin with the I/O Standard set to Differential HSTL-18 on the Cyclone® IV will result in an error in Fitting.
• When I compile an FPGA design containing Nios® II with Quartus® Prime, I get the error message "Can't generate netlist output files".
• Q] I encountered a build error in Nios® II SBT for Eclipse related to insufficient capacity of On-Chip Memory, can I work around it without changing the FPGA design?
• What is the difference between the DE0-Nano-SoC and Atlas-SoC kits?
• Licenses for Altera® FPGA Development Kits purchased through Macnica Mauser do not appear in the Licenses Held & Users tab in the License Center.
• What power source is monitored by the FPGA's internal POR (Power-On Reset) circuitry on the Stratix® 10?
• Output frequency is not changed by PLL reconfig simulation.
• For the User Flash Memory (UFM) of MAX® V, is there any specification for the change time of various signals (nbusy,valid,data) from the falling edge of nread?
• For the User Flash Memory (UFM) of MAX® V, is there an address setup/hold time provision for nread?
• There is an IP in Platform Designer called AXI / APB Translator Intel FPGA IP, can this be used to connect Avalon with AXI and APB in Platform Designer?
• Where can I find the release notes for Quartus® Prime Standard Edition v18.1?
• Where can I find the release notes for Quartus® Prime Standard Edition v18.0?
• Where can I find the release notes for Quartus® Prime Pro Edition v18.1?
• Where can I find the release notes for Quartus® Prime Pro Edition v18.0?
• Are the devices supported by the Quartus® Prime Pro Edition and Standard Edition Programmer the same?
• Is there a problem if I Program/Configure a write file created with an older Quartus® version using a higher version of Programmer?
• When I try to debug a Linux application with DS-5, I get the following error message
• Please tell me how to handle the pins on the EZ6301QI when I want to leave one of the two LDOs unused.
• How do I switch between 3G/12G on SDI II IP while in user mode?