What power source is monitored by the FPGA's internal POR (Power-On Reset) circuitry on the Stratix® 10?

The power supplies monitored by the Power-On Reset (POR) circuit on the Stratix® 10 are.

　VCC, VCCERAM, VCCPT, VCCADC, VCCIO_SDM, VCCBAT, VCCL_HPS

For more information, please refer to the following document: 
Altera® Stratix® 10 Power Management User Guide (search for Power-On Reset Circuitry)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-pwr.pdf

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Category:Specifications 
Tools:- 
Device:Stratix® 10