There is an IP in Platform Designer called AXI / APB Translator Intel FPGA IP, can this be used to connect Avalon with AXI and APB in Platform Designer?

No, this IP is an IP that the tool automatically inserts when it creates the internal bus, so it cannot be used manually by the user.

(Reference: Can I manually instantiate a Qsys Translator IP in a Qsys system? 
https://community.altera.com/kb/knowledge-base/can-i-manually-instantiate-qsys-translator-ip-in-a-qsys-system/341447

Platform Designer supports the following interfaces, which can be directly connected (automatically converted) between memory-mapped interfaces in Platform Designer. (Quartus Prime v18.1) 
・AMBA 3 AXI (version 1.0) 
・AMBA 4 AXI (version 2.0) 
・AMBA 4 AXI-Lite (version 2.0) 
・AMBA 4 AXI-Stream (version 1.0) 
・AMBA 3 APB ( (version 1.0) 
・Avalon

(Reference) 
Intel Quartus Prime Pro Edition User Guide: Platform Designer (Platform Designer Interconnect section) 
https://www.intel.com/content/www/us/en/ programmable/documentation/zcn1513987282935.html#mwh1409958828732

Intel Quartus Prime Standard Edition User Guide: Platform Designer (Designing with Avalon and AXI Interfaces section) 
https://www.intel.com/content/ www/us/en/programmable/documentation/jrw1529444674987.html#mwh1409959042128

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Category:Quartus® Prime (Platform Designer) 
Tools:Quartus® Prime 
Devices:-