FAQ

• Is it possible to simulate Remote System Upgrade IP?
• How do I enable the Tamper-Protection bit?
• Can Signal Tap be used when Tamper-Protection bit is enabled?
• Is it possible to perform simulation by combining RX/TX in a configuration where two FPGAs communicate with each other via LVDS?
• Is there any specification for temperature characteristics of phase compensation capacitance CA of EZ6301QI?
• Is it possible to reconfigure only the FPGA on an Arria® 10 SoC?
• I am using a Stratix® 10 Temperature Sensor IP with InternalTemperature Sensing Diodes (TSD), but some CHs are returning incorrect values. Why is this?
• I am using PCI Express with Cyclone® V. I am supplying 100 MHz Refclk to the FPGA, how is the external coupling and I/O standard?
• Active Serial Memory Interface (ASMI) Parallel II has multiple slaves.
• Active Serial Memory Interface (ASMI) Does the Conduit Interface pin of the Parallel II IP need to be connected to a configuration device (e.g., EPCQ) by the user?
• Is it possible to inform the FPGA side of WFI/WFE State, a Coretex-A9 feature, with Cyclone® V SoC?
• Can I use HyperLynx SI to analyze an IC at a voltage different from the voltage set in the IBIS model?
• Does the PCI-Express (PCIe) IP of the Arria® V device reflect the default settings for VOD?
• Generating and simulating a FIFO (VHDL) from IP Catalog with a data width of 1 bit results in an error.
• I am using DDR3L in the Arria® 10 EMIF with an operating frequency of 533.333MHz, should I select -1066 for the Speed Bin setting on the Mem Timing tab in the IP parameter settings, the rate corresponding to the operating frequency?
• Stratix® 10 SEU Mitigation uses an external ROM for smh file storage, is there a dedicated pin?
• The TCK frequency of the Altera® FPGA Download Cable II (USB-Blaster II) can be changed by the user. Once the frequency setting is changed, does it remain after the download cable is turned off (unplugged) or Quartus® Prime is terminated?
• Are there any commands to configure the FPGA in the U-Boot of an Arria® 10 SoC?
• Can I change the FPGA device model number without changing the EMIF (External Memory Interface) IP parameters?
• What is the default setting for Transceiver Refclk in Cyclone® V?
• Where can I find reference designs for Altera® PACs (Programmable Acceleration Cards)?
• What kind of PLL is the CMU PLL?
• What do the Recommended Speed Grades listed in the PCI Express® User's Guide for Arria® 10 mean?
• Does Arria® 10 require adherence to a power sequence?
• When reading data in the configuration device from ASMI Parallel IP Core, FFh is read.
• Does Stratix® 10 require adherence to a power sequence?
• Does the Cyclone® 10 GX require adherence to a power sequence?
• What power source is monitored by the FPGA's internal POR (Power-On Reset) circuitry in the Cyclone™ 10 GX?
• What is the maximum frequency of the clock input (clkin) to the ASMI Parallel IP Core?
• How should I think about data types in DSP Builder and FIR Filter II IP?