FAQ

• How can I estimate the number of multipliers when implementing an FIR filter in DSP Builder or FIR Compier II?
• Are there any restrictions on the use of printf statements in the OpenCL kernel?
• What happens when a Cyclone® V SoC retries to boot due to boot failure?
• Does the number of multipliers used by the DSP Builder model vary with the data width used?
• The following warning occurs when compiling a design that uses DSP blocks in Arria® 10. Please let me know the countermeasure.
• Which report can I look at to check the usage of the DSP Block?
• I am running Configuration via Protocol (CvP) on an Arria® 10 device and it fails.
• What are the MSEL and BSEL pin settings on an Arria® 10 SoC when the FPGA is configured after booting the Hard Processor System (HPS)?
• When I change the Hard Processor System (HPS) clock in Platform Designer, what should I look for to know if the change has been made?
• Can I invert the lane polarity (Polarity Inversion) on the JESD204B IP?
• The Arria® 10 SoC does not output the clock as set in the Hard Processor System (HPS) of the Platform Designer.
• I want to re-edit an IP in the IP Catalog, but the wizard won't open.
• Do you have a sample design that uses the I2C Controller on the Hard Processor System (HPS) side?
• Error when copying a project created with Quartus® Prime on a Linux machine to a Windows® PC and compiling it
• When doing isometric wiring of EMIF patterns, should the wiring delay in the package be taken into account?
• In the EMIF Layout Guidelines, there is a reference to Maximum Trace Length, but does that length include the internal wiring length of the package?
• How do I specify the DCLK frequency to be used in the AS configuration of Stratix® V/Arria® V/Cyclone® V?
• What is the behavior of bit 6 :s2f on SoC devices when set?
• Is there an example design for a 10GBASE-R SFP loopback test for the Arria® 10 SoC Development Kit?
• Is there anything I should be aware of when using multiple chip selects with the Hard Processor System (HPS) QSPI controller in a Cyclone® V SoC?
• If my license for Arm® Development Studio 5 (DS-5®) Intel® SoC FPGA edition expires, will I still be able to use the previous version?
• I generated an Example Design for 12G-SDI, changed the CDR clock frequency of SDI RX and generated RTL, but the change is not reflected.
• I get a license error for Arm® Development Studio 5 (DS-5®) SoC FPGA edition despite an expired license.
• I generated an Example Design for 12G-SDI, changed the CDR clock frequency of SDI RX and generated RTL, but the change is not reflected.
• I tried to connect the EMIF Toolkit to multiple EMIFs, but an error occurred.
• Is it possible to generate only Physical Layer with PCI-Express Protocol in Arria® 10?
• If the calibration fails in the EMIF, how do I get it to re-calibrate?
• How do I get SystemVerilog 'define constants to be recognized correctly throughout a ModelSim® project?
• For the interrupt controller (GIC) on the Hard Processor System (HPS) side of the Cyclone® V SoC, is it possible to specify the interrupt sense polarity for the interrupt signals (FPGA_IRQ0 to 63) from the FPGA side?
• I have registered multiple NICs as license servers and am using them as redundant. In this case, do all registered license servers need to be activated?