The s2f bit in the Hard Processor System (HPS) Reset Manager register of the Arria® V / Cyclone® V SoC is used to control the h2f_rst_n signal.
Normally, this bit is output when Warm Reset is issued on the HPS side, but by setting s2f in miscmodrst to '1', it is possible to control the h2f_rst_n output to the FPGA while leaving the HPS side running.
(Reference) Cyclone V HPS Memory Map
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Category: SoC
Tools: SoC EDS
Device: Arria® V / Cyclone® V