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For the interrupt controller (GIC) on the Hard Processor System (HPS) side of the Cyclone® V SoC, is it possible to specify the interrupt sense polarity for the interrupt signals (FPGA_IRQ0 to 63) from the FPGA side?

For the interrupt controller (GIC) on the Hard Processor System (HPS) side of the Cyclone® V SoC, is it possible to specify the interrupt sense polarity for the interrupt signals (FPGA_IRQ0 to 63) from the FPGA side?

  • Updated

FPGA_IRQx does not support polarity selection by register setting on the HPS side.
For Edge, prepare interrupt signals based on the rising edge (positive edge); for
Level, prepare interrupt signals based on the High level detection.

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Category: SoC
Tools: -
Device: Cyclone® V

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