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I generated an Example Design for 12G-SDI, changed the CDR clock frequency of SDI RX and generated RTL, but the change is not reflected.

I generated an Example Design for 12G-SDI, changed the CDR clock frequency of SDI RX and generated RTL, but the change is not reflected.

  • Updated

The Dynamic Reconfiguration 4 profile settings of the Native PHY connected to the SDI RX need to be changed.

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Category: SDI
Tool: Quartus® Prime
Device: Stratix® 10