Skip to main content

What are the MSEL and BSEL pin settings on an Arria® 10 SoC when the FPGA is configured after booting the Hard Processor System (HPS)?

What are the MSEL and BSEL pin settings on an Arria® 10 SoC when the FPGA is configured after booting the Hard Processor System (HPS)?

  • Updated

The BSEL pin setting for HPS boot is the pin that specifies where the boot source is located.
It should be set (pin processed) to one of the following

https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410070178831.html

(See BSEL Values for Boot Source Selection)

When configuring the FPGA after booting the HPS, the MSEL pin should be set to one of the following values (pin processing).

MSEL[2:0]=000: FPP x16 and x32 Fast POR
- MSEL[2:0]=001: FPP x16 and x32 Standard POR

https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410070178831.html

(Search for MSEL Pin Settings for Each Configuration Scheme of Arria 10 Devices)

--------------------
Category: SoC
Tools:-
Device: Arria® 10

Related articles