FAQ

• Can I use the Remote Update (RSU) feature when cascading FPGAs and configuring multiple FPGAs with one Configuration ROM?
• The reference manual lists the interrupt factors for the interrupt controller (GIC) on the Hard Processor System (HPS) side of the Cyclone® V SoC. What are the interrupts listed with Interrupt Name cpu0_deflags0~6 and cpu1_deflags0~6 caused by?
• The Early Power Estimator (EPE) of the Cyclone® V SoC cannot estimate the power consumption of 3.0V I/O on the Hard Processor System (HPS) side.
• Regarding the interrupt controller (GIC) on the Hard Processor Sytem (HPS) side of the Cyclone® V SoC, in which register should the notification destination (CPU0 or CPU1) for each interrupt be controlled?
• Regarding the interrupt controller (GIC) on the Hard Processor System (HPS) side of the Cyclone® V SoC, the reference manual lists only interrupt factors after interrupt number 32. Are interrupt numbers 0-31 not assigned anything?
• Is it possible to control nCONFIG using FPGA_Manager from the Hard Processor System (HPS) side on a Cyclone® V SoC and reconfigure the FPGA fabric side (AS mode)?
• Is there any time specified between setting the Triple Speed Ethernet (TSE) IP software reset (SW_RESET in the command_config register) to 1 and the SW reset completing?
• Does the SW_RESET sequence continue to execute after the hardware reset (reset) signal of the Triple Speed Ethernet (TSE) IP is deactivated?
• How do I sign in to My Intel (formerly My Altera)?
• I would like to obtain or renew a license for Quartus® Prime. What is the link to the Licensing Center?
• I have a myAltera account, do I need to get a new myIntel account?
• I cannot find information on Intel® FPGAs (formerly Altera) on the Intel website.
• Are there any pins on Stratix® V that are not Hot-Socket compatible?
• Are the dimensions of the Exposed Pad in the 144-pin EQFP package of the Cyclone® 10 LP all the same?
• Where can I find the code conversion table for 8B10B?
• When fitting a Verilog HDL array code in MAX® 10, the code is not inferred to RAM, but is fitted to logic.
• When simulating with a simulator such as ModelSim®, how should I describe the input signals being pulled-up on the board on the test bench?
• Where can I find information on the in-package routing delay for each pin of a device?
• When I try to start Quartus® Prime Pro Edition on a Windows® 7 PC, I get the error message "api-ms-win-crt-runtime-l1-1-0.dll not found. error message appears and the program fails to start.
• In the Native PHY settings for the Arria® 10 GX, there is a section called Common PMA Options > Transceiver Link Type: SR or LR.
• What is the purpose of the Arria® 10 SoC FPGA's early I/O release feature?
• In the Reed-Solomon II IP configuration, can I select Encoder and change the Number of symbols per codeword (codeword length N) to a setting other than "Up to 255"?
• Is it possible to configure an FPGA design that uses the FPGA2SDRAM (F2S) port on a Cyclone® V SoC / Arria® V SoC after booting Linux from the Hard Processor System (HPS) side?
• What is the maximum burst transfer size of the DMA Controller (DMA-330) built into the Hard Processor System (HPS) of a Cyclone® V SoC FPGA?
• How can I verify that the Watchdog Timer (WDT) provided as a Hard Processor System (HPS) peripheral in the Arria® 10 SoC is working?
• When using the Watchdog Timer (WDT) provided as an HPS peripheral in an Arria® 10 SoC, is it necessary to implement the WDT initial settings in a user program or something?
• The U484 package device in the Cyclone® 10 GX does not have I/O Bank 3B, but the Pin-Out file shows VCCIO3B and VREFB3BN0. How should I handle this?
• Should I include a pull-up or pull-down resistor to handle the MSEL pin on the Cyclone® 10 LP?
• How do I add an assertion to the wave window with the add wave command?
• Even if the JTAG Clock is set to 24MHz, the HPS Flash Programmer outputs logs as if it is writing at 16MHz when executing a write operation.