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When fitting a Verilog HDL array code in MAX® 10, the code is not inferred to RAM, but is fitted to logic.

When fitting a Verilog HDL array code in MAX® 10, the code is not inferred to RAM, but is fitted to logic.

  • Updated

Configuration settings for single image with MAX® 10

(Configuration mode in the Assignments menu ⇒ Device ⇒ Device and Pin Options ⇒ Configuration)

The single image is implemented in the logic element if the configuration setting is Single Compressed Image or Single Uncompressed Image in the Assignments menu ⇒ Device and Pin Options ⇒ Configuration (Configuration mode).


If this setting is Single Compressed Image with Memory Initialization or Single Uncompressed Image with Memory Initialization, it is implemented in the internal memory (M9K).

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Category: Quartus® Prime
Tools: Quartus® Prime
Device: MAX® 10

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