Cyclone V Hard Processor System Technical Reference Manual
10.3.12.2.1. GIC Interrupt Map for the Cyclone V SoC HPS
GIC numbers 32 and after are mapped to interrupts from peripherals shared by CPU0 and CPU1, called SPI (Sheared Periperal Interrupts).
GIC numbers 0 to 31 are interrupt factors that CPU0 and CPU1 have independently.
For GIC numbers (ID) 0 to 31, see
"Interrupt Distributor interrupt sources" in the Cortex-A9 MPCore Technical Reference Manual.
The mapping is as follows. (*Nothing is mapped to ID16-26)
"ID0-15: Software Generated Interrupts (SGI) ... Software Interrupts
ID27: Global timer, PPI ........ Global timer interrupt (Cortex-A9 built-in timer)
ID28: A legacy nFIQ pin, PPI ... Interrupt input to nFIQ pin (*not supported)
ID29: Private timer, PPI ....... Private timer interrupt (Cortex-A9 built-in timer)
ID30: Watchdog timers, PPI ..... Watchdog timer interrupts (Cortex-A9 built-in timer)
ID31: A legacy nIRQ pin, PPI ... Interrupt input to nIRQ pin (*not supported)."
This information is the same for Arria® V SoC and Arria® 10 SoC.
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Category: SoC
Tools: SoC EDS
Device: Cyclone® V