Regarding the interrupt controller (GIC) on the Hard Processor System (HPS) side of the Cyclone® V SoC, the reference manual lists only interrupt factors after interrupt number 32. Are interrupt nu...

Cyclone V Hard Processor System Technical Reference Manual
https://www.intel.com/content/www/us/en/programmable/documentation/sfo 1410143707420.html

(Search by GIC Interrupt Map)

GIC numbers 32 and after are mapped to interrupts from peripherals shared by CPU0 and CPU1, called SPI (Sheared Periperal Interrupts).
GIC numbers 0 to 31 are interrupt factors that CPU0 and CPU1 have independently.

For GIC numbers (ID) 0 to 31, see
"3.1.2. Interrupt Distributor interrupt sources" in the Cortex-A9 MPCore Technical Reference Manual.
http://infocenter .arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407g/CCHCEDJC.html

The mapping is as follows. (*Nothing is mapped to ID16-26)
"ID0-15: Software Generated Interrupts (SGI) ... Software Interrupts
ID27: Global timer, PPI ........ Global timer interrupt (Cortex-A9 built-in timer)
ID28: A legacy nFIQ pin, PPI ... Interrupt input to nFIQ pin (*not supported)
ID29: Private timer, PPI ....... Private timer interrupt (Cortex-A9 built-in timer)
ID30: Watchdog timers, PPI ..... Watchdog timer interrupts (Cortex-A9 built-in timer)
ID31: A legacy nIRQ pin, PPI ... Interrupt input to nIRQ pin (*not supported)."

This information is the same for Arria® V SoC and Arria 10 SoC.

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Category: SoC
Tools: SoC EDS
Device: Cyclone® V