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Regarding the interrupt controller (GIC) on the Hard Processor Sytem (HPS) side of the Cyclone® V SoC, in which register should the notification destination (CPU0 or CPU1) for each interrupt be controlled?

Regarding the interrupt controller (GIC) on the Hard Processor Sytem (HPS) side of the Cyclone® V SoC, in which register should the notification destination (CPU0 or CPU1) for each interrupt be controlled?

  • Updated

Category: SoC
Tools: SoC EDS
Device: Cyclone® V

The following registers can be used to specify the CPU to which interrupts are to be notified.

PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0416b/ Beifbdhg.html

(3.2.10. Target Registers (ICDIPTRn))

For one GIC interrupt, 8 bits are mapped, but only bits 0 and 1 are valid (meaning CPU0 and CPU1), and bits 2 and 7 are Reserved.
CPU0 only: 0x01
- CPU1 only: 0x02
- Both CPU0 and 1: 0x03 (*)

(*) PPI interrupt (Private Peripheral Interrupt) can be notified to both CPUs, but SPI interrupt
(Shared Periperal Interrupt) is not guaranteed to be notified to both CPUs.
(If one CPU clears interrupt pending first, the other CPU will not be notified of the interrupt.)

This also applies to the Arria® V SoC and Arria 10 SoC.

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Category: SoC
Tools: SoC EDS
Device: Cyclone® V

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