How can I verify that the Watchdog Timer (WDT) provided as a Hard Processor System (HPS) peripheral in the Arria® 10 SoC is working?

Please check the status of i_watchdog_0_l4wd.wdt_cr register (Address: 0xFFD00200).
Register specification:

https://www.altera.com/hps/arria-10/hps.html#reg_soc_top/sfo1429890450363.html

If bit0(wdt_en) is set to 1:Enable, WDT is enabled.
By default, bit1(rmod) is set to 0:RST, but if WDT times out with this setting, the reset will be triggered.
You can check the WDT reset operation by executing software that does not clear the WDT counter.

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Category: SoC
Tools: SoC EDS
Device: Arria® 10