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What is the maximum burst transfer size of the DMA Controller (DMA-330) built into the Hard Processor System (HPS) of a Cyclone® V SoC FPGA?

What is the maximum burst transfer size of the DMA Controller (DMA-330) built into the Hard Processor System (HPS) of a Cyclone® V SoC FPGA?

  • Updated

The maximum is 256 Byte Burst.
The DMA channel of DMA-330 has two burst setting items, dst_burst_size and dst_burst_len.
Since the size of one burst transfer is determined by dst_burst_size × dst_burst_len The maximum size is 16 Bytes x 16 data transfers = 256 Bytes, which is larger than the maximum value of each item.

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Category: SoC
Tools: -
Device: Cyclone® V

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