As a result of verification on the evaluation board, we confirmed that it is possible to re-execute the AS configuration on the FPGA side by following the procedure below.
It is possible by controlling the following registers in the FPGA Manager on the HPS side.
fpgamgrregs.ctrl register (Address: 0xFF706004)
https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#topic/sfo 1410067797617.html
<Procedure>
0. Set MSEL to AS mode in advance. 1.
1. set en bit (bit0) of fpgamgrregs.ctrl register to 0x1
This enables nCONFIG control from FPGA Manager
Set the nconfigpull bit (bit2) of the fpgamgrregs.ctrl register to 0x1
This causes nCONFIG to be pulled down and the FPGA side enters the Reset state
Set nconfigpull bit back to 0x0
This releases nCONFIG from PULL DOWN, and the FPGA side reconfigures and shifts to User Mode.
The FPGA can be reconfigured by the above procedure, but note that access to the FPGA side from
HPS will not be available during the reconfiguration.
It is necessary to take measures such as disabling the H2F and LWH2F bridges once.
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Category: SoC
Tool: SoC EDS
Device: Cyclone® V