When simulating with a simulator such as ModelSim®, how should I describe the input signals being pulled-up on the board on the test bench?

In the case of Verilog HDL, the signal to be Pull-Up is declared with the same signal name as the wire declaration.

wire data; // target signal for Pull-Up
pullup (data); //specify Pull-Up on board (including Weak Pull-up inside FPGA)

Note: This description can only be used on the testbench (simulation).

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Category: Simulation
Tools: ModelSim®
Devices: -