FAQ

• Are there any regulations in controlling HPS_nPOR and HPS_nRST of the Arria® 10 SoC?
• Can ARMCC 6 provided in SoC EDS v17.1 be used with Cyclone® V SoC?
• Is it possible to write directly from JTAG to an eMMC connected to the SD/MMC controller on the Hard Processor System (HPS) side of the Cyclone® V SoC, similar to QSPI / NAND?
• When designing with the DSP Builder Standard Blockset and attempting to convert the design to HDL using Signal Compiler, an error occurred during the Analyze DSP Builder System stage.
• Is it possible to control the oscillation frequency in 100Hz steps by Frequency Modulation input using NCO IP?
• Are there any functional differences between Preloader and Minimal Preloader (MPL)?
• Is it possible to control GPIOs on the Hard Processor System (HPS) side of the Cyclone® V SoC / Arria V SoC from circuitry on the FPGA side?
• What is the Thread Capacity listed in the OpenCL report?