Does not include the internal wiring of the package.
The values in the layout guidelines indicate the ball-to-ball distance between the FPGA and the memory, and do not include the internal wiring length of the package regardless of whether the package deskew is on or off.
Also, it does not necessarily have to meet the layout guideline as long as the timings are met.
(In addition, when inputting the Board Skew Parameter in the EMIF IP GUI, add the delay caused by the internal wiring length when the Package deskew is On.)
(Reference) External Memory Interface Handbook Volume 2: Design Guidelines
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/ literature/hb/external-memory/emi_plan.pdf
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Category: External Memory Interface
Tools: -
Devices: -