Generating and simulating a FIFO (VHDL) from IP Catalog with a data width of 1 bit results in an error.

＜Error Message

Fatal: (vsim-3807) Types do not match between component and entity for port "sample_data".

In the generated FIFO description, sample_data is created with "sample_data: IN STD_LOGIC_VECTOR (0 DOWNTO 0);" and STD_LOGIC_VECTOR. LOGIC in the upper hierarchy, this error occurs due to a port mismatch.

When connecting the signal std_logic_vector(0 downto 0) in the lower hierarchy with std_logic in the upper hierarchy in VHDL,

　　a(0) => b

and connect it by adding (0).

-------------------- 
Category: Simulation 
Tools: ModelSim® Intel® FPGA Edition 
Devices: -