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I would like to verify that the Hard Processer System's SPI verification can be connected in a loopback and send/receive correctly. Can I connect the SPI interface from the Hard Processor System (HPS) and use it as a conduit in Platform Designer?

I would like to verify that the Hard Processer System's SPI verification can be connected in a loopback and send/receive correctly. Can I connect the SPI interface from the Hard Processor System (HPS) and use it as a conduit in Platform Designer?

  • Updated

If you use the SPI built into the HPS of Cyclone® V, you can check the software operation using the loopback function built into the SPI itself, using the SRL bit in the CTRL0 register.

When using this method, the output destination in the Platform Designer of the HPS should be the FPGA, not the HPS I/O.
This way, you can export signals outside of Platform Designer. Loop it back through RTL.

The exported signals can also be observed by SignalTap.

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Category: SoC
Tools: SoC EDS
Device: Cyclone® V

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