Please note the following
- The two EMIF IPs should be generated separately without copying.
However, in Platform Designer, there is no problem to generate two EMIF implementations.
For V series (Stratix® V, Arria® V, Cyclone® V), you need to run pin_assignment.tcl for each EMIF. But copying the EMIF does not generate two pin_assignmnet.tcl
- Set the Board Skew values properly for the two EMIF IPs.
The FPGA pin-to-memory distance may be different for the two EMIFs, please check
--------------------
Category: External Memory Interface
Tools: Quartus® Prime
Devices: -