Abstract PHY has the following differences compared to the regular model
-The normal PHY-external memory path is replaced with a model that includes an internal memory array
-The Nios II processor is disabled and replaced with HDL for simulation
-The need for full-speed clock simulation events is eliminated.
For more information, please refer to the following documents
External Memory Interfaces Arria 10 FPGA IP User Guide
https://docs.altera.com/r/5ybDUDNrbPzSEVSGXW2L4g/asedmW48siA2DllJBsKZLA
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Category: External Memory Interface
Tool: Quartus® Prime
Device: Arria® 10