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I am performing a PCI-Express (PCIe) design using Stratix® 10 devices. We are using Quartus® Prime v18.1 Pro Edition and are experiencing a "Minimum Pulse Width" violation in our timing analysis.

I am performing a PCI-Express (PCIe) design using Stratix® 10 devices. We are using Quartus® Prime v18.1 Pro Edition and are experiencing a "Minimum Pulse Width" violation in our timing analysis.

  • Updated

As of v18.1, the "Minimum Pulse Width" violation can be ignored. 
Please wait until a future version of the Tool fixes this issue.

（Why is a minimum pulse width timing violation information message reported during the compilation of the Intel® Stratix® 10 Hard IP for PCI Express*? IP Core version 18.1? 
https://community.altera.com/kb/knowledge-base/why-is-a-minimum-pulse-width-timing-violation-information-message-reported-durin/345391

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Category: PCI-Express 
Tools: Quartus® Prime 
Device: Stratix® 10

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